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preliminary 18-mb qdr?-ii sram two-word burst architecture cy7c1310v18 cy7c1312v18 cy7c1314v18 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05180 rev. *a revised august 2, 2002 features ? separate independent read and write data ports ? supports concurrent transactions 167-mhz clock for high bandwidth two-word burst on all accesses double data rate (ddr) interfaces on both read & write ports (data transferred at 333 mhz) @ 167mhz two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only two output clocks (c and c ) accounts for clock skew and flight time mismatches echo clocks (cq and cq ) simplify data capture in high speed systems single multiplexed address input bus latches address inputs for both read and write ports separate port selects for depth expansion synchronous internally self-timed writes available in x8, x18, and x36 configurations 1.8v core power supply with hstl inputs and outputs 13x15 mm 1.0-mm pitch fbga package, 165 ball (11x15 matrix) variable drive hstl output buffers extended hstl output voltage (1.4v?v dd ) jtag interface on-chip delay lock loop (dll) configurations cy7c1310v18 ? 2m x 8 cy7c1312v18 ? 1m x 18 cy7c1314v18 ? 512k x 36 functional description the cy7c1310v18/cy7c1312v18/cy7c1314v18 are 1.8v synchronous pipelined srams, equipped with qdr ? -ii archi- tecture. qdr tm -ii architecture consists of two separate ports to access the memory array. the read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. qdr tm -ii architecture has separate data inputs and data outputs to completely eliminate the need to ? turn-around ? the data bus required with common i/o devices. access to each port is accomplished through a common address bus. the read address is latched on the rising edge of the k clock and the write address is latched on the rising edge of the k clock. accesses to the qdr tm -ii read and write ports are completely independent of one another. in order to maximize data throughput, both read and write ports are equipped with double data rate (ddr) interfaces. each address location is associated with two 8-bit words (cy7c1310v18) or 18-bit words (cy7c1312v18) or 36-bit words (cy7c1314v18) that burst sequentially into or out of the device. since data can be transferred into and out of the device on every rising edge of both input clocks (k/k and c/c ), memory bandwidth is maximized while simplifying system design by eliminating bus ? turn-arounds. ? depth expansion is accomplished with port selects for each port. port selects allow each port to operate independently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the c/c (or k/k in a single clock domain) input clocks. writes are conducted with on-chip synchronous self-timed write circuitry. logic block diagram (cy7c1310v18) clk a (19:0) gen. k k control logic address register d [7:0] read add. decode read data reg. rps wps q [7:0] control logic address register reg. reg. reg. 8 20 8 16 8 bws [1:0] v ref write add. decode 8 a (19:0) 20 c c 8 1m x 8 array 1m x 8 array write reg write reg cq cq 8
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 2 of 25 selection guide [1] 200 mhz 167 mhz 133 mhz unit maximum operating frequency 200 167 133 mhz maximum operating current tbd tbd tbd ma note: 1. shaded cells indicate advanced information. logic block diagram (cy7c1312v18) clk a (18:0) gen. k k control logic address register d [17:0] read add. decode read data reg. rps wps q [17:0] control logic address register reg. reg. reg. 18 19 18 36 18 bws [1:0] v ref write add. decode 18 a (18:0) 19 c c 18 512k x 18 array 512k x 18 array write reg write reg cq cq 18 logic block diagram (cy7c1314v18) clk a (17:0) gen. k k control logic address register d [35:0] read add. decode read data reg. rps wps q [35:0] control logic address register reg. reg. reg. 36 18 36 72 36 bws [3:0] v ref write add. decode 36 a (17:0) 18 c c 36 256k x 36 array 256k x 36 array write reg write reg cq cq 36
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 3 of 25 pin configurations cy7c1310v18 (2m x 8) - 11 x 15 bga 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc v ss /72m a bws 1 k wps nc nc nc nc nc nc tdo nc nc d5 nc nc nc tck nc nc a nc k bws 0 v ss aaa nc v ss v ss v ss vss v dd a v ss v ss v ss v dd q4 nc v ddq nc nc nc nc q7 a v ddq v ss v ddq v dd v dd q5 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d4 v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss c nc q6 nc d7 d6 v dd a 891011 nc av ss /36m rps cq a nc nc q3 v ss nc nc d3 nc v ss nc q2 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq d1 v ddq nc q1 nc v ddq v ddq nc v ss nc d0 nc tdi tms v ss a nc a nc d2 nc zq nc q0 nc nc nc nc a cy7c1312v18 (1m x 18) - 11 x 15 bga 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc v ss /144m nc/36m bws 1 k wps nc q9 d9 nc nc nc tdo nc nc d13 nc nc nc tck nc d10 a nc k bws 0 v ss aaa q10 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q11 d12 v ddq d14 q14 d16 q16 q17 a v ddq v ss v ddq v dd v dd q13 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d11 v ss nc v ss q12 nc v ref v ss v dd v ss v ss a v ss c nc q15 nc d17 d15 v dd a 891011 q0 av ss /72m rps cq a nc nc q8 v ss nc q7 d8 nc v ss nc q6 d5 nc nc v ref nc q3 v ddq nc v ddq nc q5 v ddq v ddq v ddq d4 v ddq nc q4 nc v ddq v ddq nc v ss nc d2 nc tdi tms v ss a nc a d7 d6 nc zq d3 q2 d1 q1 d0 nc a
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 4 of 25 pin configurations (continued) 234 567 1 a b c d e f g h j k l m n p r a cq q27 d27 d28 d34 doff q33 v ss /288m nc/72m bws 2 k wps bws 1 q18 d18 q30 d31 d33 tdo q28 d29 d22 d32 q34 q31 tck d35 d19 a bws 3 k bws 0 v ss aaa q19 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q20 d21 v ddq d23 q23 d25 q25 q26 a v ddq v ss v ddq v dd v dd q22 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d20 v ss q29 v ss q21 d30 v ref v ss v dd v ss v ss a v ss c q32 q24 q35 d26 d24 v dd a 891011 q0 nc/36m v ss /144m rps cq a d17 q17 q8 v ss d16 q7 d8 q16 v ss d15 q6 d5 d9 q14 v ref q11 q3 v ddq q15 v ddq d14 q5 v ddq vddq v ddq d4 v ddq d12 q4 q12 v ddq v ddq d11 v ss d10 d2 q10 tdi tms v ss a q9 a d7 d6 d13 zq d3 q2 d1 q1 d0 q13 a cy7c1314v18 (512k x 36) - 11 x 15 bga
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 5 of 25 pin definitions pin name i/o pin description d [x:0] input- synchronous data input signals, sampled on the rising edge of k and k clocks during valid write operations . cy7c1310v18 - d[7:0] cy7c1312v18 - d[17:0] cy7c1314v18 - d[35:0] wps input- synchronous write port select, active low . sampled on the rising edge of the k clock. when asserted active, a write operation is initiated. deasserting will deselect the write port. deselecting the write port will cause d [x:0] to be ignored. bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2 and 3 ? active low . sampled on the rising edge of the k and k clocks during write operations. used to select which byte is written into the device during the current portion of the write operations. bytes not written remain unaltered. cy7c1310v18 ? bws 0 controls d [3:0] and bws 1 controls d [7:4] . cy7c1312v18 ? bws 0 controls d [8:0] and bws 1 controls d [17:9]. cy7c1314v18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] and bws 3 controls d [35:27] all the byte writes are sampled on the same edge as the data. deselecting a byte write select will cause the corresponding byte of data to be ignored and not written into the device. a input- synchronous address inputs. sampled on the rising edge of the k clock during active read and write operations. these address inputs are multiplexed for both read and write operations. internally, the device is organized as 2m x 8 (2 arrays each of 1m x 8) for cy7c1310v18, 1m x 18 (2 arrays each of 512k x 18) for cy7c1312v18 and 256k x 36 (2 arrays each of 256k x 36) for cy7c1314v18. therefore, only 20 address inputs are needed to access the entire memory array of cy7c1310v18, 19 address inputs for cy7c1312v18 and 18 address inputs for cy7c1314v18. these inputs are ignored when the appro- priate port is deselected. q [x:0] outputs- synchronous data output signals . these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read operations or k and k . when in single clock mode. when the read port is deselected, q [x:0] are automatically three-stated. cy7c1310v18 ? q [7:0] cy7c1312v18 ? q [17:0] cy7c1314v18 ? q [35:0] rps input- synchronous read port select, active low . sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasserting will cause the read port to be deselected. when deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the c clock. each read access consists of a burst of two sequential transfers. c input- clock positive output clock input . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. c input-clock negative output clock input . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. k input-clock positive input clock input . the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input-clock negative input clock input . k is used to capture synchronous inputs being presented to the device and to drive out data through q [x:0] when in single clock mode. cq echo clock cq is referenced with respect to c . this is a free running clock and is synchronized to the output clock of the qdr tm -ii. in the single clock mode, cq is generated with respect to k. the timings for the echo clocks are shown in the ac timing table. cq echo clock cq is referenced with respect to c . this is a free running clock and is synchronized to the output clock of the qdr tm -ii. in the single clock mode, cq is generated with respect to k . the timings for the echo clocks are shown in the ac timing table.
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 6 of 25 introduction functional overview the cy7c1310v18/cy7c1312v18/cy7c1314v18 are synchronous pipelined burst srams equipped with both a read port and a write port. the read port is dedicated to read operations and the write port is dedicated to write operations. data flows into the sram through the write port and out through the read port. these devices multiplex the address inputs in order to minimize the number of address pins required. by having separate read and write ports, the qdr tm -ii completely eliminates the need to ? turn-around ? the data bus and avoids any possible data contention, thereby simplifying system design. each access consists of two 8-bit data transfers in the case of cy7c1310v18, two 18-bit data transfers in the case of cy7c1312v18 and two 36-bit data transfers in the case of cy7c1314v18, in one clock cycles. accesses for both ports are initiated on the rising edge of the positive input clock (k). all synchronous input timings are referenced from the rising edge of the input clocks (k and k ) and all output timings are referenced to the output clocks (c and c or k and k when in single clock mode). all synchronous data inputs (d [x:0] ) inputs pass through input registers controlled by the input clocks (k and k ). all synchronous data outputs (q [x:0] ) outputs pass through output registers controlled by the rising edge of the output clocks (c and c or k and k when in single clock mode). all synchronous control (rps , wps , bws [x:0] ) inputs pass through input registers controlled by the rising edge of the input clocks (k and k ). the following descriptions take cy7c1312v18 as an example. however, the same is true for the other qdr tm -ii srams, cy7c1310v18 and cy7c1314v18. these chips utilize a delay lock loop (dll) that is designed to function between 80 mhz and the specified maximum clock frequency. the dll may be disabled by applying ground to the doff pin. read operations the cy7c1312v18 is organized internally as a 512kx36 sram. accesses are completed in a burst of two sequential 18-bit data words. read operations are initiated by asserting rps active at the rising edge of the positive input clock (k). the address is latched on the rising edge of the k clock. the address presented to address inputs is stored in the read address register. following the next k clock rise the corre- sponding lowest order 18-bit word of data is driven onto the q [17:0] using c as the output timing reference. on the subse- quent rising edge of c, the next 18-bit data word is driven onto zq input output impedance matching input . this input is used to tune the device outputs to the system data bus impedance. q [x:0] output impedance are set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternately, this pin can be connected directly to v dd , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. doff input dll turn off. connecting this pin to ground will turn off the dll inside the device. the timings in the dll turned off operation will be different from those listed in this data sheet. more details on this operation can be found in the application note, ? dll operation in the qdr tm -ii. ? tdo output tdo for jtag . tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc input no connects inside the package . can be tied to any voltage level. nc/36m input address expansion for 36m . this is not connected to the die and so can be tied to any voltage level. nc/72m input address expansion for 72m . this is not connected to the die and so can be tied to any voltage level. v ss /72m input address expansion for 72m . this must be tied low on the 18m devices. v ss/ 144m input address expansion for 144m . this must be tied low on the 18m devices. v ss/ 288m input address expansion for 288m . this must be tied low on the 18m devices. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs and outputs as well as ac measurement points. v dd power supply power supply inputs to the core of the device . should be connected to 1.8v power supply. v ss ground ground for the device . should be connected to ground of the system. v ddq power supply power supply inputs for the outputs of the device . should be connected to 1.5v power supply. pin definitions (continued) pin name i/o pin description
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 7 of 25 the q [17:0] . the requested data will be valid 0.4 ns from the rising edge of the output clock (c/c , 167-mhz device). synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the output clocks (c/c ). this will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. write operations write operations are initiated by asserting wps active at the rising edge of the positive input clock (k). on the same k clock rise, the data presented to d [17:0] is latched and stored into the lower 18-bit write data register provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ), the address is latched and the infor- mation presented to d [17:0] is stored into the write data register provided bws [1:0] are both asserted active. the 36 bits of data are then written into the memory array at the specified location. when deselected, the write port will ignore all inputs after the pending write operations have been completed. byte write operations byte write operations are supported by the cy7c1312v18. a write operation is initiated as described in the write operation section above. the bytes that are written are determined by bws 0 and bws 1 which are sampled with each set of 18-bit data word. asserting the appropriate byte write select input during the data portion of a write will allow the data being presented to be latched and written into the device. deasserting the byte write select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. this feature can be used to simplify read/modify/write operations to a byte write operation. single clock mode the cy7c1312v18 can be used with a single clock that controls both the input and output registers. in this mode, the device will recognize only a single pair of input clocks (k and k ) that control both the input and output registers. this operation is identical to the operation if the device had zero skew between the k/k and c/c clocks. all timing parameters remain the same in this mode. to use this mode of operation, the user must tie c and c high at power on. this function is a strap option and not alterable during device operation. concurrent transactions the read and write ports on the cy7c1312v18 operate completely independently of one another. since each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the trans- action on the other port. also, reads and writes can be started in the same clock cycle. if the ports access the same location at the same time, the sram will deliver the most recent infor- mation associated with the specified address location. this includes forwarding data from a write cycle that was initiated on the previous k clock rise. depth expansion the cy7c1312v18 has a port select input for each port. this allows for easy depth expansion. both port selects are sampled on the rising edge of the positive input clock only (k). each port select input can deselect the specified port. deselecting a port will not affect the other port. all pending transactions (read and write) will be completed prior to the device being deselected. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matching with a tolerance of 10% is between 175 ? and 350 ? , with v ddq = 1.5v. the output impedance is adjusted every 1024 cycles to adjust for drifts in supply voltage and temperature. echo clocks echo clocks are provided on the qdr tm -ii to simplify data capture on high-speed systems. two echo clocks are generated by the qdr tm -ii. cq is referenced with respect to c and cq is referenced with respect to c . these are free-running clocks and are synchronized to the output clock of the qdr tm -ii. in the single clock mode, cq is generated with respect to k and cq is generated with respect to k . the timings for the echo clocks are shown in the ac timing table.
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 8 of 25 \ application example [2] truth table [ 3, 4, 5, 6, 7, 8] operation k rps wps dq dq write cycle: load address on the rising edge of k clock; input write data on k and k rising edges. l-h x l d(a + 00)at k(t) d(a + 01) at k (t) read cycle: load address on the rising edge of k clock; wait one and a half cycle; read data on c and c rising edges. l-h l x q(a + 00) at c (t + 1) q(a + 01) at c(t + 2) nop: no operation l-h h h high-z high-z standby: clock stopped stopped x x previous state previous state write cycle descriptions (cy7c1310v18 and cy7c1312v18) [3, 9] bws 0 bws 1 kk comments lll-h ? during the data portion of a write sequence : cy7c1310v18 ? both nibbles (d [7:0] ) are written into the device, cy7c1312v18 ? both bytes (d [17:0] ) are written into the device. ll ? l-h during the data portion of a write sequence : cy7c1310v18 ? both nibbles (d [7:0] ) are written into the device, cy7c1312v18 ? both bytes (d [17:0] ) are written into the device. notes: 2. the above application shows 4 cy7c1312v18 being used. this holds true for cy7c1310v18 and cy7c1314v18 as well. 3. x = ? don't care, ? h = logic high, l= logic low, represents rising edge. 4. device will power-up deselected and the outputs in a three-state condition. 5. ? a ? represents address location latched by the devices when transaction was initiated. a+00, a+01 represents the internal address sequence in the burst. 6. ? t ? represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectivel y succeeding the ? t ? clock cycle. 7. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 8. it is recommended that k = k and c = c = high when clock is stopped. this is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 9. assumes a write cycle was initiated per the write port cycle description truth table. bws 0 and bws 1 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved. d q add. k/k c/c cntr. add. k/k c/c cntr. 18 72 sram #1 sram #4 v term = v ref 72 18 clk/clk (output) q din add. cntr. clk/clk (input) 18 18 2 r = 50 ? v t = v ref r = 50 ? d q memory controller 17 17 2
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 9 of 25 lhl-h ? during the data portion of a write sequence : cy7c1310v18 ? only the lower nibble (d [3:0] ) is written into the device. d [7:4] will remain unaltered, cy7c1312v18 ? only the lower byte (d [8:0] ) is written into the device. d [17:9] will remain unaltered. lh ? l-h during the data portion of a write sequence : cy7c1310v18 ? only the lower nibble (d [3:0] ) is written into the device. d [7:4] will remain unaltered, cy7c1312v18 ? only the lower byte (d [8:0] ) is written into the device. d [17:9] will remain unaltered. hll-h ? during the data portion of a write sequence : cy7c1310v18 ? only the upper nibble (d [7:4] ) is written into the device. d [3:0] will remain unaltered, cy7c1312v18 ? only the upper byte (d [17:9] ) is written into the device. d [8:0] will remain unaltered. hl ? l-h during the data portion of a write sequence : cy7c1310v18 ? only the upper nibble (d [7:4] ) is written into the device. d [3:0] will remain unaltered, cy7c1312v18 ? only the upper byte (d [17:9] ) is written into the device. d [8:0] will remain unaltered. hhl-h ? no data is written into the devices during this portion of a write operation. hh ? l-h no data is written into the devices during this portion of a write operation. write cycle descriptions (cy7c1314v18) [3, 9] bws 0 bws 1 bws 2 bws 3 kk comments l l l l l-h - during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l l l l - l-h during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l-h - during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] will remain unaltered. l h h h - l-h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] will remain unaltered. h l h h l-h - during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will remain unaltered. h l h h - l-h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will remain unaltered. h h l h l-h - during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will remain unaltered. h h l h - l-h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will remain unaltered. h h h l l-h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unaltered. write cycle descriptions (cy7c1310v18 and cy7c1312v18) (continued) [3, 9] bws 0 bws 1 kk comments
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 10 of 25 h h h l - l-h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unaltered. h h h h l-h - no data is written into the device during this portion of a write operation. h h h h - l-h no data is written into the device during this portion of a write operation. write cycle descriptions (cy7c1314v18) (continued) [3, 9] bws 0 bws 1 bws 2 bws 3 kk comments
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 11 of 25 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage on v dd relative to gnd........ ? 0.5v to +2.9v dc voltage applied to outputs in high-z state [12] ............................... ? 0.5v to v ddq + 0.5v dc input voltage [12] ............................ ? 0.5v to v ddq + 0.5v current into outputs (low)......................................... 20 ma static discharge voltage.......................................... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature [10] v dd v ddq com ? l 0 c to +70 c 1.8 100 mv 1.4v to v dd electrical characteristics over the operating range [1, 11] parameter description test conditions min. typ. max. unit v dd power supply voltage 1.7 1.8 1.9 v v ddq i/o supply voltage 1.4 1.5 v dd v v oh output high voltage i oh = ? 2.0 ma, nominal impedance v ddq ? 0.2 v ddq ? 0.2 v ddq v v ol output low voltage i ol = 2.0 ma, nominal impedance v ss v ss 0.2 v v ih input high voltage [12] v ref + 0.1 v ref + 0.1 v ddq +0.3 v v il input low voltage [12] ? 0.3 v ref ? 0.1 v ref ? 0.1 v i x input load current gnd v i v ddq ? 5 ? 5 5 a i oz output leakage current gnd v i v ddq, output disabled ? 5 ? 5 5 a v ref input reference voltage [13] typical value = 0.75v 0.68 0.75 0.95 v i dd v dd operating supply x8, x18 v dd = max., i out = 0 ma, f = f max = 1/t cyc 133 mhz tbd ma 167 mhz tbd ma 200 mhz tbd ma i dd v dd operating supply x36 v dd = max., i out = 0 ma, f = f max = 1/t cyc 133 mhz tbd ma 167 mhz tbd ma 200 mhz tbd ma i sb1 automatic power-down current, x8, x18 max. v dd , both ports deselected, v in v ih or v in v il f = f max = 1/t cyc, inputs static 133 mhz tbd ma 167 mhz tbd ma 200 mhz tbd ma i sb1 automatic power-down current, x36 max. v dd , both ports deselected, v in v ih or v in v il f = f max = 1/t cyc, inputs static 133 mhz tbd ma 167 mhz tbd ma 200 mhz tbd ma notes: 10. ambient temperature = t a . this is the case temperature. 11. all voltage referenced to ground. 12. overshoot: v ih (ac)< v dd + 0.5v for t < t tcyc /2; undershoot v il (ac)< ? 0.5v for t < t tcyc /2; power-up: v ih <1.8v and v dd <1.8v and v ddq < 1.4v for t < 200 ms. 13. v ref min. = 0.68v or 0.46v ddq , whichever is larger, v ref max. = 0.95v or 0.54v ddq , whichever is smaller.
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 12 of 25 switching characteristics over the operating range [1, 14] 200 mhz 167 mhz 133 mhz parameter description min. max. min. max. min. max. unit t cyc k clock and c clock cycle time 5.0 6.0 6.0 7.5 7.5 8.0 ns t kh input clock (k/k and c/c ) high 2.0 -2.4-3.0- ns t kl input clock (k/k and c/c ) low 2.0 -2.4-3.0- ns t khkh k/k clock rise to k /k clock rise and c/c to c/c rise (rising edge to rising edge) 2.2 - 2.7 - 3.38 - ns t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0.0 2.3 0.0 2.8 0.0 3.5 ns set-up times t sa address set-up to k clock rise 0.5 -0.6-0.7- ns t sc control set-up to clock (k, k ) rise (rps , wps , bws 0 , bws 1 ) 0.5 -0.6-0.7- ns t sd d [17:0] set-up to clock (k and k ) rise 0.5 -0.6-0.7- ns hold times t ha address hold after clock (k and k ) rise 0.5 -0.6-0.7- ns t hc control hold after clock (k and k ) rise (rps , wps , bws 0 , bws 1 ) 0.5 -0.6-0.7- ns t hd d [17:0] hold after clock (k and k ) rise 0.5 -0.6-0.7- ns output times t co c/c clock rise (or k/k in single clock mode) to data valid [14] - 0.38 - 0.40 - 0.40 ns t doh data output hold after output c/c clock rise (active to active) ? 0.38 - ? 0.40 - ? 0.40 - ns t ccqo c/c clock rise to echo clock valid - 0.36 - 0.38 - 0.38 ns t cqoh echo clock hold after c/c clock rise ? 0.36 - ? 0.38 - ? 0.38 - t cqd echo clock high to data change 0.38 0.40 0.40 t clz clock (c and c ) rise to low-z [15, 16] ? 0.38 - ? 0.40 - ? 0.40 - ns t chz clock (c and c ) rise to high-z (active to high-z) [15, 16] - 0.38 - 0.40 - 0.40 ns dll timing t kc clock phase jitter - 0.13 - 0.15 - 0.15 ns t kc lock dll lock time (k, c) 1024 - 1024 - 1024 - cycles capacitance [17] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 1.8v v ddq = 1.5v tbd pf c clk clock input capacitance tbd pf c o output capacitance tbd pf notes: 14. unless otherwise noted, test conditions assume signal transition time of 2 v/ns, timing reference levels of 0.75v, v ref = 0.75v, rq = 250 ? , v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads. 15. t chz , t clz , are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 100 mv from steady-state voltage. 16. at any given voltage and temperature t chz is less than t clz and t chz less than t co . 17. tested initially and after any design or process change that may affect these parameters.
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 13 of 25 ac test loads and waveforms 1.25v 0.25v r = 50 ? 5pf including jig and scope all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75v v ref = 0.75v [14] 0.75v under te st 0.75v device under te s t output 0.75v v ref v ref output zq zq (a) rq = 250 ? (b) rq = 250 ? slew rate = 2v / ns switching waveforms = don ? t care = undefined read/deselect sequence k k a data out rps b a q(a) q(a+1) q(b) q(b+1) c q(c) q(c+1) t kh t kl t cyc t sa t ha t sc t hc t chz t kh t kl t khkh t doh t khkh c c t co t clz cq cq t cqoh t cqd t khch t khch t co t ccqo t cqoh t ccqo t kl t kl t kh t kh t khkh t cqd read read read deselect deselect deselect
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 14 of 25 notes: 18. c and c reference to data outputs and do not affect write operations. 19. bws x low = valid, byte writes allowed, see byte write table for details. switching waveforms k = don ? t care = undefined write/deselect sequence [18, 19] k a data in wps a d(a) d(a+1) d(b) d(b+1) b t kh t kl t cyc t sa t hd t sc t hd t sd bws x t sc t hc t kl t hc t ha write deselect write deselect deselect deselect
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 15 of 25 ieee 1149.1 serial boundary scan (jtag) the qdr tm -ii devices incorporate a serial boundary scan test access port (tap) in the fbga package. this port operates in accordance with ieee standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 1.8v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up note: 20. bws[0:x] is low during these cycles. switching waveforms k wps = don ? t care = undefined read/write/deselect sequence [20] k a q [x:0] rps d [x:0] d c b q(a) q(a+1) d(b) d(b+1) d(e) d(e+1) d(d) d(d+1) q(c) q(c+1) q(e) q(g+1) a q(e+1) q(f) q(f+1) q(a+1) a c c cq cq read/write read/write e e f read/write read deselect deselect
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 16 of 25 in a reset state which will not interfere with the operation of the device. test access port ? test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see instruction codes). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture ir state, the two least significant bits are loaded with a binary ? 01 ? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction code table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address, data or control signals into the sram and cannot preload the input or output buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather it performs a capture of the input and output ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. extest is not implemented in the tap controller, and therefore this device is not compliant to the 1149.1 standard. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample / preload instruction has been loaded.
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 17 of 25 idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not implemented, so the tap controller is not fully 1149.1 compliant. when the sample/preload instructions loaded into the instruction register and the tap controller in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller ? s capture set-up plus hold times (t cs and t ch ). the sram clock inputs might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the k, k , c and c captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 18 of 25 note: 21. the 0/1 next to each state represents the value at tms at the rising edge of tck. tap controller state diagram [21] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 19 of 25 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms tap electrical characteristics over the operating range [11, 12, 22, 23 ] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 2.0 ma v dd ? 0.45 v v oh2 output high voltage i oh = ? 100 a v dd ? 0.2 v v ol1 output low voltage i ol = 2.0 ma 0.45 v v ol2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 0.65v dd v dd + 0.3 v v il input low voltage ? 0.3 0.35v dd v i x input and outputload current gnd v i v dd ? 5 5 a notes: 22. these characteristic pertain to the tap inputs (tms, tck, tdi and tdo). parallel load levels are specified in the electrical characteristics table. 23. v dd means core supply voltage.
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 20 of 25 tap ac switching characteristics over the operating range [24, 25] parameter description min. max. unit t tcyc tck clock cycle time 100 ns t tf tck clock frequency 10 mhz t th tck clock high 40 ns t tl tck clock low 40 ns set-up times t tmss tms set-up to tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns notes: 24. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 25. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 21 of 25 tap timing and test conditions [25] (a) tdo c l = 20 pf z 0 = 50 ? gnd 0.9v 50 ? 1.8v 0v all input pulses 0.9v test clock test mode select tck tms test data-in tdi test data-out t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdov t tdox tdo identification register definitions instruction field cy7c1310v18 cy7c1312v18 cy7c1314v18 description 2m x 8 1m x 18 512k x 36 revision number (31:29) 000 000 000 version number. cypress device id (28:12) 11010011010000101 11010011010010101 11010011010100101 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1 1 1 indicates the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 22 of 25 instruction codes instruction code description extest 000 captures the input/output ring contents. places the boundary scan register between the tdi and tdo. this instruction is not 1149.1 compliant. the extest command implemented by these devices will not place the output buffers into a high-z condition. if the output buffers need to be in high-z condition, this can be accomplished by deselecting the read port. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/output contents. places the boundary scan register between tdi and tdo. the sample z command implemented by these devices will place the output buffers into a high-z condition. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. boundary scan order bit # bump id 0 6r 1 6p 2 6n 3 7p 4 7n 5 7r 6 8r 7 8p 8 9r 9 11p 10 10p 11 10n 12 9p 13 10m 14 11n 15 9m 16 9n 17 11l 18 11m 19 9l 20 10l 21 11k 22 10k 23 9j 24 9k 25 10j 26 11j 27 11h 28 10g 29 9g 30 11f 31 11g 32 9f 33 10f 34 11e 35 10e 36 10d 37 9e 38 10c 39 11d 40 9c 41 9d 42 11b 43 11c 44 9b 45 10b 46 11a 47 10a 48 9a 49 8b boundary scan order (continued) bit # bump id
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 23 of 25 50 7c 51 6c 52 8a 53 7a 54 7b 55 6b 56 6a 57 5b 58 5a 59 4a 60 5c 61 4b 62 3a 63 2a 64 1a 65 2b 66 3b 67 1c 68 1b 69 3d 70 3c 71 1d 72 2c 73 3e 74 2d 75 2e 76 1e 77 2f 78 3f 79 1g 80 1f 81 3g 82 2g 83 1j 84 2j 85 3k 86 3j 87 2k 88 1k 89 2l 90 3l 91 1m 92 1l 93 3n boundary scan order (continued) bit # bump id 94 3m 95 1n 96 2m 97 3p 98 2n 99 2p 100 1p 101 3r 102 4r 103 4p 104 5p 105 5n 106 5r boundary scan order (continued) bit # bump id
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 24 of 25 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram qdr rams and quad data rate rams comprise a new family of products developed by cypress, hitachi, idt, micron, nec, and samsung technology. all product and company names mentioned in this document are the trademarks of their respective holders. ordering information [1] speed (mhz) ordering code package name package type operating range 200 cy7c1310v18-200bzc bb165a 13 x 15 mm fbga commercial cy7c1312v18-200bzc cy7c1314v18-200bzc 167 cy7c1310v18-167bzc bb165a 13 x 15 mm fbga commercial cy7c1312v18-167bzc CY7C1314V18-167BZC 133 cy7c1310v18-133bzc bb165a 13 x 15 mm fbga commercial cy7c1312v18-133bzc cy7c1314v18-133bzc 165-ball fbga (13 x 15 x 1.2 mm) bb165a 51-85122-*b
preliminary cy7c1310v18 cy7c1312v18 cy7c1314v18 document #: 38-05180 rev. *a page 25 of 25 document title: cy7c1310v18/cy7c1312v18/cy7c1314v18 18-mb qdr ? -ii sram two-word burst architecture document number: 38-05180 rev. ecn no. issue date orig. of change description of change ** 110859 11/09/01 skx new data sheet *a 115917 08/05/02 rcs changed status to preliminary. removed 250 mhz speed bin. shaded 200 mhz speed bin. added 133 mhz speed bin. updated jtag scan order.

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